1. Field of the Invention
This invention relates to computers and more particularly to addressing of computer memories.
2. Description of the Related Art
Dynamic Random Access Memories (DRAMs) require that the addresses provided to them be split between row and columns. The row address is provided to the DRAM during a first time period and is latched into the DRAM on assertion of the row access strobe (RAS). The column address is multiplexed onto the bus and is latched into the DRAM during a second time period on assertion of the column access strobe (CAS). That address multiplexing allows, e.g., a twenty bit address to be provided to the DRAM using only 10 address pins. DRAMs with various arrangements of row and column addresses are known in the art. For instance, symmetric DRAMs have the same number of bits for rows as for columns. Asymmetric DRAMs have more of either row or column bits than the other. The number of bits in the row and column depends upon the size of the DRAM.
Many DRAM controllers exist to support the different DRAM sizes and configurations. One way DRAM controllers address DRAMs is as follows. Assume a processor has a twenty bit addressing capability (20 bits) and a 256K DRAM, requiring 18 address bits, A18-A1, is connected to the processor. The 256K DRAM has 9 address pins, MA8-MA0. The processor could connect 9 sequential address pins, e.g., A18-A10 to the DRAM. The processor provides the most significant address bits A18-A10, as the row address and the bits A9-A1 as the column address. Table 1 shows the address bits provided to the DRAM on each DRAM address pin MA8-MA0 and which processor pin (PROC PIN) is used to connect to the DRAM.
TABLE 1 ______________________________________ DRAM MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 PIN PROC A18 A17 A16 A15 A14 A13 A12 A11 A10 PIN ROW A18 A17 A16 A15 A14 A13 A12 A11 A10 COL- A9 A8 A7 A6 A5 A4 A3 A2 A1 UMN ______________________________________
As shown in Table 1, address bits A18 and A9 are provided on the same pin processor pin (A18) to DRAM pin (MA8).
For a different size DRAM, e.g., 1 Mbyte, a 20 bit address may be multiplexed as shown in Table 2.
TABLE 2 __________________________________________________________________________ DRAM PIN MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 PROC PIN A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 ROW A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 COLUMN A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 __________________________________________________________________________
Table 2, shows that the DRAM controller needs to support a different address multiplexing scheme for the 20 bit address. For instance, A10 has become a column address in Table 2 as compared to a row address in Table 1 and is multiplexed onto pin A20 rather than A10. Additionally, all the other pairs of address bits multiplexed onto an address line have also changed. Thus, the DRAM controller has to provide different configurations in order to support different sizes of DRAMs. Specifically, at a minimum, a DRAM controller has to be able to multiplex different address bits onto multiple output pins and provide appropriate control logic. It would be desirable to be able to support varying DRAM sizes without having to provide the additional logic and levels of control necessary to support varying sizes of DRAMs by the prior art schemes discussed.